use ieee.std_logic_1164.all;
-- use ieee.std_logic_unsigned.all; ENTITY b2bcdvtn IS
PORT
(sygnały wej/wyj);
END b2bcdvtn;
ARCHITECTURE structure OF b2bcdvtn IS
COMPONENT r1_v IS
COMPONENT r2_v IS
-- COMPONENT r3_v;
COMPONENT lk_v IS
COMPONENT us_v IS
COMPONENT r4_v IS
SIGNAL nazwa
: STD_LOGIC;
SIGNAL nazwa
: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
R1 : r1_v PORT MAP
(lista przyporządkowań);
R2 : r2_v PORT MAP
(lista przyporządkowań);
R3 : r2_v PORT MAP
(lista przyporządkowań);
LK : lk_v PORT MAP
(lista przyporządkowań);
US : us_v PORT MAP
(lista przyporządkowań);
R4 : r4_v PORT MAP
(lista przyporządkowań);
END structure;
use ieee.std_logic_1164.all;
-- use ieee.std_logic_unsigned.all; ENTITY b2bcdvtn IS
PORT
(
LB
: IN
STD_LOGIC_VECTOR(7 DOWNTO 0); CK
: IN
STD_LOGIC;
CLK
: IN
STD_LOGIC;
START : IN
STD_LOGIC;
CLOCK : OUT
STD_LOGIC;
STOP
: OUT
STD_LOGIC;
LD
: OUT
STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END b2bcdvtn;
ARCHITECTURE structure OF b2bcdvtn IS
Deklaracje komponentów;
Dodatkowe deklaracje sygnałów; BEGIN
Podstawienia komponentów; END structure;
Deklaracje komponentów COMPONENT r1_v IS
PORT
(
LB
: IN
STD_LOGIC_VECTOR(7 DOWNTO 0); LOAD : IN
STD_LOGIC;
CK
: IN
STD_LOGIC;
ROUT : OUT
STD_LOGIC;
RB
: OUT
STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT r1_v;
COMPONENT r2_v IS
PORT
(
RIN
: IN
STD_LOGIC;
LOAD : IN
STD_LOGIC;
CK
: IN
STD_LOGIC;
ROUT : OUT
STD_LOGIC;
DB
: OUT
STD_LOGIC_VECTOR(3 downto 0)
);
END COMPONENT r2_v;
COMPONENT lk_v IS
PORT
(
CK
: IN
STD_LOGIC;
LOAD : IN
STD_LOGIC;
--
L
: OUT
STD_LOGIC_VECTOR(3 DOWNTO 0); STOP : OUT
STD_LOGIC
);
END COMPONENT lk_v;
COMPONENT us_v IS
PORT
(
CLK
: IN
STD_LOGIC;
START
: IN
STD_LOGIC;
STOP
: IN
STD_LOGIC;
CLOCK
: OUT
STD_LOGIC;
LOAD
: OUT
STD_LOGIC
);
END COMPONENT us_v;
COMPONENT r4_v IS
PORT
(
STOP : IN
STD_LOGIC;
CLK
: IN
STD_LOGIC;
DB
: IN
STD_LOGIC_VECTOR(3 DOWNTO 0); DA
: IN
STD_LOGIC_VECTOR(3 DOWNTO 0); LD
: OUT
STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT r4_v;
SIGNAL ROUT1
: STD_LOGIC;
SIGNAL ROUT2
: STD_LOGIC;
SIGNAL ROUT3
: STD_LOGIC;
SIGNAL LOAD
: STD_LOGIC;
SIGNAL STP
: STD_LOGIC;
SIGNAL D2
: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL D3
: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL RB
: STD_LOGIC_VECTOR(7 DOWNTO 0);
Podstawienie komponentów BEGIN
R1 : r1_v PORT MAP
(LB=>LB,
LOAD=>LOAD,
CK=>CK,
ROUT=>ROUT1,
RB=>RB
);
R2 : r2_v PORT MAP
(RIN=>ROUT1,
LOAD=>LOAD,
CK=>CK,
ROUT=>ROUT2,
DB=>D2
);
R3 : r2_v PORT MAP
(RIN=>ROUT2,
LOAD=>LOAD,
CK=>CK,
--
ROUT=>
DB=>D3
);
LK : lk_v PORT MAP
(CK=>CK,
LOAD=>LOAD,
STOP=>STP
);
US : us_v PORT MAP
(CLK=>CLK,
START=>START,
STOP=>STP,
CLOCK=>CLOCK,
LOAD=>LOAD
);
R4 : r4_v PORT MAP
(STOP=>STP,
CLK=>CLK,
DB=>D2,
DA=>D3,
LD=>LD
);
STOP <= STP;
END structure;
use ieee.std_logic_1164.all; ENTITY r1_v IS
PORT
(
LB
: IN
STD_LOGIC_VECTOR(7 DOWNTO 0); LOAD
: IN
STD_LOGIC;
CK
: IN
STD_LOGIC;
ROUT
: OUT STD_LOGIC;
RB
: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END r1_v;
ARCHITECTURE r1 OF r1_v IS
BEGIN
PROCESS (CK,LOAD)
VARIABLE QB : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
IF (LOAD = '1') THEN
QB := LB;
ELSIF (CK'EVENT AND CK = '1') THEN
QB(7 DOWNTO 1) := QB(6 DOWNTO 0); QB(0) := '0';
END IF;
RB
<=
QB;
IF (QB(7) = '1') THEN
ROUT <= '1';
ELSE
ROUT <= '0';
END IF;
END PROCESS;
END r1;
use ieee.std_logic_1164.all; ENTITY r2_v IS
PORT
(
RIN
: IN
STD_LOGIC;
LOAD
: IN
STD_LOGIC;
CK
: IN
STD_LOGIC;
ROUT
: OUT
STD_LOGIC;
DB
: OUT
STD_LOGIC_VECTOR(3 downto 0)
);
END r2_v;
ARCHITECTURE r2 OF r2_v IS
SIGNAL QDB
: STD_LOGIC_VECTOR(3 downto 0); BEGIN
PROCESS (CK,LOAD)
BEGIN
IF (LOAD = '1') THEN
QDB <= (others =>'0'); ELSIF (CK'EVENT AND CK = '1') THEN
QDB(0) <= RIN;
QDB(1) <= (not QDB(3) and not QDB(2) and QDB(0)) or (QDB(2) and QDB(1) and not QDB(0)) or (QDB(3) and not QDB(0)); QDB(2) <= (not QDB(2) and QDB(1)) or (QDB(1) and QDB(0)) or (QDB(3) and not QDB(0));
QDB(3) <= (QDB(2) and not QDB(1) and not QDB(0)) or (QDB(3) and QDB(0));
END IF;
ROUT
<=
QDB(3) or (QDB(2) and QDB(1)) or (QDB(2) and QDB(0)); DB <= QDB;
END PROCESS;
END r2;
b
b
b
out
b’
b’
b’
b’
3
2
1
0
3
2
1
0
0
0
0
0
0
0
0
0
0
IN
1
0
0
0
1
0
0
0
1
IN
2
0
0
1
0
0
0
1
0
IN
3
0
0
1
1
0
0
1
1
IN
4
0
1
0
0
0
1
0
0
IN
5
0
1
0
1
1
0
0
0
IN
6
0
1
1
0
1
0
0
1
IN
7
0
1
1
1
1
0
1
0
IN
8
1
0
0
0
1
0
1
1
IN
9
1
0
0
1
1
1
0
0
IN
use ieee.std_logic_1164.all; ENTITY r4_v IS
PORT
(
STOP
: IN
STD_LOGIC;
CLK
: IN
STD_LOGIC;
DB
: IN
STD_LOGIC_VECTOR(3 DOWNTO 0); DA
: IN
STD_LOGIC_VECTOR(3 DOWNTO 0); LD
: OUT
STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END r4_v;
ARCHITECTURE r4 OF r4_v IS
BEGIN
PROCESS (CLK,STOP)
VARIABLE QLD : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (STOP = '1') THEN
QLD(7 DOWNTO 4) := DA;
QLD(3 DOWNTO 0) := DB;
END IF;
END IF;
LD
<=
QLD;
END PROCESS;
END r4;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY lk_v IS
PORT
(
CK
: IN
STD_LOGIC;
LOAD
: IN
STD_LOGIC;
L
: OUT
STD_LOGIC_VECTOR(3 DOWNTO 0); STOP
: OUT
STD_LOGIC
);
END lk_v;
ARCHITECTURE lk OF lk_v IS
SIGNAL
stp
: STD_LOGIC;
BEGIN
PROCESS (CK,LOAD)
VARIABLE
cnt
: STD_LOGIC_VECTOR(3 DOWNTO 0);
--RANGE 0 TO 15;
BEGIN
IF (LOAD = '1') THEN
cnt := "0000";
ELSIF (CK'EVENT AND CK = '1') THEN
cnt := cnt + '1';
END IF;
L
<=
cnt;
IF (cnt = "1000") THEN
stp <= '1';
ELSE
stp <= '0';
END IF;
STOP <= stp;
END PROCESS;
END lk;