9_Timers_2010-WWW

Podstawy techniki

mikroprocesorowej

ETEW006

Układy czasowo – licznikowe

Andrzej Stępień

Katedra Metrologii Elektronicznej i Fotonicznej

Pralka - pomiary i sterowanie

pomiar

•

nienia:

stopie

napełnienia wod

bna, p

kni

cia w

ęż

•

temperatury:

wody, pary wodnej

•

czasu:

dozowanie

rodka pior

cego, momentu rozpocz

cia prania

•

stotliwo

ci: pr

dko

ść

obrotowa silnika

wywa

enie b

bna (statyczny czujnik przyspieszenia)

sygnalizacja d

kowa (buzzer)

sterowanie

•

wietlacza LCD i przycisków (klawiatury)

•

pami

ci programów prania i własnych programów u

ytkownika

•

zaworu wlotowego wody, pompki odprowadzania wody

•

silnika, grzałki, zamkni

cia drzwi, agregatu pary, systemu zraszania

•

czem szeregowym przy aktualizacji programów prania

Jak to zrobić

zlicza

pojedyncze impulsy

i paczki impulsów ?

mierzy

czas

, cz

stotliwo

ść

i przesuni

cie fazy

φφφφ

wygenerowa

pojedynczy sygnał prostok

tny o zadanym okresie

współczynniku wypełnienia

ττττ

= ½ ?

wygenerowa

pojedynczy sygnał prostok

tny o programowalnym

okresie

i współczynniku wypełnienia

ττττ

wygenerowa

kilka synchronicznych sygnałów prostok

tnych o

programowalnych okresach

i współczynnikach wypełnienia

ττττ

uzyska

sygnał stałopr

dowy o programowalnej warto

redniej

stworzy

zmienny sygnał o zało

onych parametrach (kształt, amplituda i

okres) ?

STM8S Timers

RM0016. STM8S microcontroller family. Reference manual.

STMicroelectronics, Doc ID 14587, Rev 6. 2009, p.128

up to

three different timer types

•

advanced control (TIM1),

•

general purpose (TIM2/ TIM3/TIM5),

•

basic timers (TIM4/TIM6).

STM8S
Advanced Control Timer 1 (TIM1)

RM0016. STM8S microcontroller family. Reference manual.

STMicroelectronics, Doc ID 14587, Rev 6. 2009, p.132

consists of a

16-bit

up-down auto-reload counter driven by a programmable

prescaler – timer may be used for a variety of purposes, including:

•

time

base

generation

•

measuring

the

pulse lengths

of input signals (input capture),

•

generating output waveforms

(output compare, PWM and one pulse mode),

•

interrupt capability

on various events (capture, compare, overflow, break,

trigger),

•

synchronization

with TIM5/TIM6 timers or external signals (external clock,

reset, trigger and enable).

Timer is

ideally suited

for a wide range of control applications, including those

requiring center-aligned PWM capability with complementary outputs and
deadtime insertion.

Timer clock can be sourced from internal clocks or from an external source

selectable through a configuration register.

STM8S
Timer 1

Figure 28. TIM1 general block diagram

STM8S
Timer 1 Base Unit

RM0016. STM8S microcontroller family. Reference manual.

STMicroelectronics, Doc ID 14587, Rev 6. 2009, p.135

Figure 29. Time base unit

prescaler

is based on a 16-bit counter

prescaler divide the counter clock frequency by any factor between 1..65536:

CK_CNT

= f

CK_PSC

/(PSCR[15:0]

+ 1

)

Prescaler

STM8S
Timer 1 in 16-bit Up Counting Mode

RM0016. STM8S microcontroller family. Reference manual.

STMicroelectronics, Doc ID 14587, Rev 6. 2009, p.137

Auto-Reload

Register

Figure 31. Counter in

Up-Counting Mode

counter counts from 0 to a user-defined compare
value (content of the TIM1_ARR register)

Set Interrupt Flag (UIF bit in TIM1_SR1 register)

Overflow

Figure 29. Time base unit

STM8S
Timer 1 in 16-bit Down Counting Mode

RM0016. STM8S microcontroller family. Reference manual.

STMicroelectronics, Doc ID 14587, Rev 6. 2009, p.139

Auto-Reload

Register

Figure 29. Time base unit

Underflow

Set Interrupt Flag

(UIF bit in TIM1_SR1 register)

Figure 34. Counter in

Down-Counting

Mode

•

counter counts from the auto-reload
value (content of the TIM1_ARR register)
down to 0

•

restarts from the auto-reload value and
generates a counter underflow

STM8S - Timer 1
in 16-bit Up/Down Counting Mode

RM0016. STM8S microcontroller family. Reference manual.

STMicroelectronics, Doc ID 14587, Rev 6. 2009, p.141

Auto-Reload

Register

Figure 29. Time base unit

Overflow

Underflow

Overflow

Underflow

Figure 37. Counter in

Up/Down-Counting Mode

(center-aligned)

MSP430FG618
Timer_A3 Features

Timer_A3 is a 16-bit timer/counter

with three capture/compare registers.

Timer_A3 can support multiple capture/compares

PWM outputs, and

interval timing

. Timer_A also has extensive interrupt capabilities. Interrupts

may be generated from the counter on overflow conditions and from each of
the capture/compare registers.

Timer_A3 features include

•

Asynchronous 16-bit timer/counter with four operating modes

•

Selectable and configurable clock source

•

Three or five configurable capture/compare registers

•

Configurable outputs with PWM capability

•

Asynchronous input and output latching

•

Interrupt vector register for fast decoding of all Timer_A interrupts

MSP430FG618
Timer_A3 Block Diagram

Timer/Counter
Continuous Mode

Timer/Counter repeatedly counts up to ValueMax and restarts from zero:

•

ValueMax = 0FFh for 8-bit

•

ValueMax = 0FFFFh for 16-bit Timer

•

ValueMax = 0FFFF FFFFh for 32-bit Timer

Divider

1/K

Clock

Select

CLK

EXTERN

CLK

LOW

CLK

FAST

Timer

CLK

CLR

Prescale

Counter

Overflow

N-bit Timer/Counter

INTERRUPT

Clear

Timer/Counter
Gating Control

Divider

1/K

Clock

Select

CLK

EXTERN

CLK

LOW

CLK

FAST

Timer

CLK

CLR

Prescale

Counter

Overflow

N-bit Timer/Counter

INTERRUPT

Clear

Gate

Timer

CLK

Gate

Timer

CLK

Standard C51
Zliczanie impulsów

P1 P2 P1

P1 P2 P1 P2

P1 P2 P1 P2 P1 P2

P1 P2 P1 P2

P1 P2

P2 P1 P2

1 cykl maszynowy

zewn

trzne

wej

cie licznika

T0 lub T1

INC
rejestru licznika

ττττ

Zliczenie zewn

trznego

impulsu na wej

ciu

licznika T0 lub T1:

> T

< f

OSC

/24

STM8S
Timers Characteristics

Symbol

Parameter

Min Typ Max

Unit

w(ICAP)in

Input capture pulse time

MASTER

res(TIM)

Timer resolution time

MASTER

Res

TIM

Timer resolution with 16-bit counter

bit

Timer resolution with 8-bit counter

bit

COUNTER

Counter clock period when internal
clock is selected

MASTER

MAX_COUNT

Maximum possible count with
16-bit counter

65,536 t

MASTER

Maximum possible count with
8-bit counter

256

MASTER

RM0016. STM8S microcontroller family. Reference manual.

STMicroelectronics, Doc ID 14587, Rev 6. 2009, p.128

MASTER

– Internal clock

C51 — stan licznika

• wpisywana warto

ść

do licznika : 0x0100

• czas trwania instrukcji:

MOV addr, #dana

; 2 cykle maszynowe

CLR

TR0

; 1 cykl maszynowy

MOV

TMOD, #1

; tryb 1 (16-bitowy) obu liczników

MOV

TL0, #LOW StanPoczT0

; StanPoczT0:

MOV

TH0,#HIGH StanPoczT0

;

00FDh

00FEh

SETB

TR0

MOV

TL0, #00

MOV

TH0,#01

CLR

TR0

; stan

Stop1:

; licznika T0:

0103h

MOV

TL0, #LOW StanPoczT0

MOV

TH0,#HIGH StanPoczT0

SETB

TR0

MOV

TH0,#01

MOV

TL0, #00

CLR

TR0

; stan

Stop2:

; licznika T0:

0201h

0101h

Wpis/odczyt synchroniczny

• programowy wpis synchroniczny

– zatrzymanie licznika na czas wpisu

– korekta wpisywanej warto

ci o czas wpisu,

zatrzymania, uruchomienia licznika

– wpis cz

ęś

ci mniej znacz

cej

– wpis cz

ęś

ci bardziej znacz

cej

– ponowne uruchomienie licznika

licznik
zatrzymany

ATmega8 — Timer/Counter
Accessing 16-bit Registers

Write

; Set TCNT1 to 0x01FF

LDI

R17, 0x01

LDI

R16, 0xFF

OUT TCNT1H, R17

; TempReg

←

R17,

high byte first

OUT TCNT1L, R16

; TCNT1L

←

R16,

low byte second

; TCNT1H

←

TempReg

Read

; Read TCNT1 into R17:R16

R16, TCNT1L

; TempReg

←

TCNT1H,

low byte first

R17, TCNT1H

; R17

←

TempReg,

high byte second

ATmega8(L). 8-bit AVR with 8K Bytes In-System Programmable Flash.

Atmel Co. 2486T–AVR–05/08, p.79

unsigned int i;
.................
TCNT1 = 0x1FF; /* Set TCNT1 to 0x01FF */
.................
i = TCNT1;

/* Read TCNT1 into i */

.................

Reading 16-bit Timer 1 Counter Register
(TIM1_CNTR)

RM0016. STM8S microcontroller family. Reference manual.

STMicroelectronics, Doc ID 14587, Rev 6. 2009, p.136

An 8-bit buffer is
implemented for the read:

Software must read the MS
byte first, after which the LS
byte value is buffered
automatically – this buffered
value remains unchanged
until the 16-bit read
sequence is completed.

no buffering when writing to the Timer 1 Counter Register (TIM1_CNTR)

Timer 1 Counter Register (TIM1_CNTRH & TIM1_CNTRL) can be written at
any time, so it is suggested not to write a new value into the counter while it is
running to avoid loading an incorrect intermediate content.

Figure 30

Writing 16-bit Timer 1 Auto-Reload
Register (TIM1_ARR)

RM0016. STM8S microcontroller family. Reference manual.

STMicroelectronics, Doc ID 14587, Rev 6. 2009, p.136

16-bit values are loaded in the Timer 1 Auto-Reload Register
(TIM1_ARR) through preload registers

This must be performed by two write instructions, one for each byte – the
MS byte must be written first.

The shadow register update is blocked as soon as the MS byte has been
written, and stays blocked until the LS byte has been written (do not use
the LDW instruction as this writes the LS byte first which produces
incorrect results)

Timer/Counter
Compare Mode

compare Timer/Counter contents with Compare Register

Divider

1/K

Clock

Select

CLK

EXTERN

CLK

LOW

CLK

FAST

CLR

Prescale

Counter

Overflow

N-bit Comparator Register

Clear

N-bit Timer/Counter

Timer

CLK

N-bit Comparator

EQU

MSP430FG618
Timer_A3 Block Diagram

MSP430FG618
Timer_A3 Compare

TAIFG
(Timer
overflow
Interrupt
FlaG)

Capture/
/Compare
Interrupt
FlaG)
CCIFG

Divider
1/2/4/8

(ID)

16-bit
Timer

ACLK

(32 768 Hz)

(External)

TACLK

SMCLK

(Sub-System

Master Clock)

16-bit

Comparator

16-bit

Compare Reg

TACCR0

MODE

(MC)

Clock Source Select

(TASSEL)

TASSEL

TAIFG

Timer_A Control Register

(TACTL)

CCIFG

Timer_A Capture/Compare
Control Register

(TACCTL0)

MSP430FG618
Timer_A3 Up-Mode

Figure 15−2. Up Mode

MSP430x4xx Family. User’s Guide.

Texas Instruments, SLAU056J, January 2010, page 15-6

Figure 15−3. Up Mode Flag Setting

Set TAIFG

Set CCIFG

in TACCR0

MSP430FG618
Timer_A3 Up Mode

Stepping
Motors

Douglas W. Jones: Stepping Motors Fundamentals. AN907.

Microchip Technology Inc. 2004, DS00907A

FIGURE 2: UNIPOLAR STEPPER MOTOR

Winding 1a: 100010001000

Winding 1b: 001000100010

Winding 2a: 010001000100

Winding 2b: 000100010001

time

Winding 1a: 110011001100

Winding 1b: 001100110011

Winding 2a: 011001100110

Winding 2b: 100110011001

time

only half of

each winding is

energized at a

time in the left

sequence

brushless

load independent

ink jet printers

CNC machines

volumetric pumps ....

magnetized rotor

stator holds multiple windings

MSP430FG618
Timer_A3 Continuous Mode

MSP430x4xx Family. User’s Guide.

Texas Instruments, SLAU056J, January 2010, page 15-8

can be used to

generate independent time intervals

and

output

frequencies

each time an

interval is completed

, an

interrupt is generated

next time

interval is

added

to the

TACCRx

in the interrupt

service routine

time interval is controlled by hardware

not software

, without impact

from interrupt latency

up to

three (Timer_A3) or five (Timer_A5) independent time intervals

output frequencies

can be generated using capture/compare

registers

MSP430FG618
Timer_A3 Continuous Mode - Example

MSP430x4xx Family. User’s Guide.

Texas Instruments, SLAU056J, January 2010, page 15-8

Figure 15−6. Continuous Mode Time Intervals

MSP430FG618
Timer_A3 Up/Down Mode

MSP430x4xx Family. User’s Guide.

Texas Instruments, SLAU056J, January 2010, page 15-10

for example, to avoid overload conditions,

two outputs driving

an H-bridge

must never be in a high state simultaneously

dead

= t

timer

∗∗∗∗

(TACCR1 − TACCR2)

With: t

dead

Time during which both outputs need to be inactive

timer

Cycle time of the timer clock

TACCRx Content of capture/compare register x

up/down
mode

supports
applications
that require

dead times
between
output
signals

Silniki DC i BLDC

Silnik pr

du stałego (

direct

urrent Motor):

•

klasyczny komutator mechaniczny, uzwojony wirnik

•

stojan z magnesami stałymi

•

przeł

czanie mi

dzy poszczególnymi fazami uzwojenia wirnika poprzez

osadzone na wale wirnika pr

ty komutatora i nieruchome szczotki w

obudowie stojana

•

wł

czanie przez szczotki kolejnych faz uzwojenia w czasie obrotu wirnika,

stały moment obrotowy i ci

gł

prac

silnika

•

zalety: niskie koszty produkcji, łatwe sterowanie

•

wady: wysoka emisja zakłóce

elektromagnetycznych

Silnik bezszczotkowy (

rush

ess

direct

urrent Motor):

•

uzwojenie stojana

•

pole magnetyczne wytwarzane przez wiruj

ce magnesy stałe

•

mechaniczny układ komutatora zast

piony elektronicznym falownikiem

•

zalety: wysoka trwało

ść

ograniczona trwało

ło

ysk (20 krotnie),

precyzyjna regulacja obrotów (zamiast silników krokowych)

•

wady: wysoka cena (2-3 krotnie), skomplikowane sterowanie

Sensorless Brushless DC Motor Control

(1/3)

AP08019. Sensorless Brushless DC Motor Control. Using Infineon 8-bit XC866 Microcontroller.

Application Note, V1.0, Oct 2006, Infineon Technologies

Sensorless Brushless DC Motor Control

(2/3)

Figure 3.
Operation of a
BLDC motor

Figure 4.

back-emf and

Inverter Signals

Sensorless Brushless DC Motor Control

(3/3)

Figure 5.

Phase Voltages

Timer/Counter
Reload Mode

write Timer/Counter value when overflow

Divider

1/K

Clock

Select

CLK

EXTERN

CLK

LOW

CLK

FAST

Timer

CLK

CLR

Prescale

Counter

Overflow

N-bit Reload Register

Clear

N-bit Timer/Counter

INTERRUPT

C517A: Tryb Reload

TF2

Rejestr CRC

P1.5
T2EX

Licznik T2

Mode 0

Mode 1

CRC

- warto

ść

pocz

tkowa licznika T2

przepełnienie

Pulse Width Modulation

(1/2)

modulacja szeroko

impulsu

ττττ

warto

ść ś

rednia napi

cia:

∗

ττττ

U(t)

ττττ

U(t)

rednieniu

Pulse Width Modulation

(2/2)

warto

ść ś

rednia napi

cia:

∗

ττττ

generator sygnału

U(t)

ττττ

U(t)

C517A: Tryb 0 Compare

Generowanie

sygnału

sinusoidalnego:

90 150 210 270 330

U(t)

U(t

) = 128 + 127

∗

sin ( 360

+ 30

)

i = 0, 1, .. , 5

port P1

np. P1.2/CC2:

U(t

192 255 192

+ filtr

dolnoprzepustowy

128

warto

chwilowe
do CC2

okres
do CRC

Timer/Counter
Capture Mode

read Timer/Counter value in the fly

Divider

1/K

Clock

Select

CLK

EXTERN

CLK

LOW

CLK

FAST

Timer

CLK

CLR

Prescale

Counter

Overflow

N-bit Capture Register

Capture

Select

Clear

N-bit Timer/Counter

write to Register

rising edge

falling edge

signal

MSP430FG4618
Capture

used to record time events

– can be used for speed computations or time

measurements.

capture inputs CCIxA and CCIxB are connected to external pins

internal signals (selected with the CCISx bits)

CMx bits select the capture edge of the input signal as rising, falling, or
both

– capture occurs on the selected edge of the input signal

if a capture occurs

•

timer value is copied into the TACCRx register

•

interrupt flag CCIFG is set

•

input signal level can be read at any time via the CCI bit

MSP430x4xx family devices may have different signals connected to
CCIxA and CCIxB

MSP430x4xx Family. User’s Guide.

Texas Instruments, SLAU056J, January 2010, page 15-11

MSP430xxx
Capture - Example

Murugavel Raju: Ultrasonic Distance Measurement With the MSP430.

Application Report. Texas Instruments, SLAA136A, October 2001

speed of sound in air at room temperature to be 1100 ft/s (~335 m/s)

MSP430 drives the transmitter transducer with a 12-cycle burst of
40-kHz square-wave signal

derived from the crystal oscillator, and the

receiver transducer receives the echo

Timer_A

in the MSP430 is configured to

count the 40-kHz crystal

frequency

such that the time measurement resolution is 25

s, which is

more than adequate for this application

measurement time base is very stable as it is derived from a quartz-
crystal oscillator

MSP430xxx
Capture - Example

echo received

by the

receiver transducer is

amplified

by an

operational

amplifier

and the amplified

output is

fed

to the

Comparator_A input

Comparator_A

senses the

presence of the echo signal
at its input and

triggers a

capture of Timer_A

count

value to

capture compare

register CCR1

12-cycle

echo

PCA - Features

(1/2)

The

PCA

consists of a :

• dedicated 16-bit counter/timer
• five 16-bit capture/compare modules
• each capture/compare module has its own associated I/O line (CEXn)
• I/O lines are routed through the Crossbar to Port I/O when enabled.

Each capture/compare module

may be configured to operate independently

in one of six modes:

• Edge-Triggered Capture
• Software Timer, High-Speed Output,
• Frequency Output,
• 8-Bit PWM
• 16-Bit PWM

The

PCA is configured and controlled

through the system controller's

Special Function Registers (SFR).

PCA - Features

(2/2)

SYSCLK/12
SYSCLK/4
T0 Overflow
SYSCLK
Ext Clock/8

Capture

Compare
Module 0

Capture

Compare
Module 1

Capture

Compare
Module 2

Capture

Compare
Module 3

Capture

Compare
Module 4

WDT

ECI

CEX0

CEX1

CEX2

CEX3

CEX4

Crossbar

Port I/O

PCA

CLOCK

MUX

max rate

SYSCLK/4

16-Bit Counter/Timer